For Lab2 you saw how to do tri-state signal using instantiated library tri-state buffers. While this may be an intuitive way of doing it (especially for those used to schematics) it is not very portable; objects like 'lpm_bustri' are Altera-specific.

A better way to achieve the same functionality is to specify the full behaviour of an output in a VHDL equation, and let the synthesis infer tri-state buffers. For example, let's say that we have a 16-bit signal called 'word' (this could be a register, buffer, or anything else that drives these wires). We want to drive a 16-bit INOUT 'databus' only when some other logic has determined that it is safe to drive the bus. Assume we have a signal called 'ok_to_drive_bus' defined somewhere (e.g. in a state machine). We could now write the following equation:

databus <= (others => 'Z') when ok_to_drive_bus = '0' else word;

This says that when 'ok_to_drive_bus' is false (i.e. our output enable should be off) then databus is set to a 16-bit 'Z', otherwise it is driven with the value of 'word'. This equation is simpler than using instantiation and is more portable, but takes a little getting used to since there is no explicit tri-state buffer.

If you look inside the Report File generated during compilation, you can look at the final synthesized logic equations for 'databus' and see how the VHDL above has been converted into real (in silicon) tri-states.

The sample solution for Lab2 that we will be posting uses this style of tri-state, so you can look it over to see how it gets used in a real design.

We recommend you use this style of tri-state. Once you have wrapped your mind around it, it is much simpler and clearer. The instantiation method is not wrong, though, so you can continue to use it if you prefer.

Robin

-- Robin Grindley (grindley@eecg.toronto.edu), January 29, 1999