Many of you asked me to post something regarding the contents of the midterm. The test will be on the labs and the materials that are discussed in the lectures up to and including the lecture on Feb. 22nd. This will include the first two topics that are posted on the web as course contents (excluding PCI). If you understood all the materials in the lectures and the lab, you will be fine. For those of you who didn't attend some of the lectures, I have posted some references on the web page and also the PS of some of the materials discussed in the lectures.
The highlight of the materials are:
ASM charts
VHDL (at the lab level)
Timing issues (metastability, clock skew)
min-max timing analysis
buses (synch/asynch)
68000 bus and bus interface design
bus arbitration
DMA (as an example of bus arbitration)

-- Alireza Kaviani (kaviani@eecg.toronto.edu), February 27, 1999