This may be a stupid question but how do we do subtraction in VHDL?? I'm not sure how to decrement the Count variable by 2.

-- Stumpey (stumped@ecf.toronto.edu), March 10, 1999

Answers

In case anyone is still looking for an answer to this, you can *not* by default treat STD_LOGIC_VECTORs as if they were numbers (with operators like + or -.) If you use the following library:

USE ieee.std_logic_unsigned.all;

then it becomes legal to do

count <= count + 2; -- count is STD_LOGIC_VECTOR

Robin

-- Robin Grindley (grindley@eecg.toronto.edu), March 13, 1999.